Most integrated circuits (ICs) are packaged in plastic or ceramic packages with extending metal leads for soldering to a printed circuit board (PCB) or for insertion into a socket. In most cases, a single package will only contain a single IC, although multiple chips are more commonly being manufactured within a single package. The use of such packages results in a low circuit density as the ceramic or plastic package consumes relatively large areas of the mounting surface, particularly if a socket is used.
Multi-chip module (MCM) technology has been developed to suit applications where it is necessary to reduce the size of the assembly or where speed or electrical noise considerations require shorter connecting leads. A typical MCM package combines a number of individual or unpackaged integrated circuits and directly attaches them to the mounting surface, for example ceramic substrate, PCB or other substrate. ICs within MCM assemblies can be electrically connected using various bonding techniques such as solder, wire bonding, tape automated bonding (TAB), and flip-chip technologies.
Many MCM assemblies are constructed in a two dimensional array to reduce the associated surface area required if the individual packaged devices were mounted on electronic circuit boards. More sophisticated MCM techniques employ three-dimensional IC layer stacking to achieve higher circuit density by further reducing the volume of interconnections. The principle drawback of most existing three dimensional MCM assembly configurations is that they interconnect vertically stacked IC layers using common carriers or conductors which typically extend vertically and/or horizontally from the stacked IC layers.
The presence of these common carriers within the MCM package significantly reduces the volumetric efficiency of the overall assembly. Further, the presence of common carriers lengthens the signal path between the circuit layers, which increases trace impedances. Such impedances can adversely affect analog circuit gain and give rise to improper RC time constants for digital circuits. Finally, the longer signal path may create stray cross-talk and electrical noise for high frequency MCM applications.
Reference is made to FIGS. 1a to 1e, which show cross sectional side views of various conventional three dimensional MCM prior art assemblies that employ well known electrical connection techniques. The figures consist of diagrammatic representations excerpted from "Three Dimensional Electronics Packaging", a multi-client study by TechSearch International, Inc. 1993. Common elements between the various MCM assemblies will be denoted by the same numerals and new features will be denoted by new numbers where appropriate.
FIG. 1a illustrates the use of well-known TAB techniques to connect four unpackaged identically sized ICs 10 to each other as well as to a PCB 12. This type of MCM assembly is described in U.S. Pat. No. 5,138,438 issued Aug. 11, 1992 to Masayuki et al., which provides an MCM assembly for memory application using TAB technology to electrically connect stacked identically sized ICs.
TAB technology is a process which joins unpackaged ICs using patterned metal on polymeric tape, applied to the ICs using any of various bonding techniques including thermocompression, thermosonic, laser or pulsed reflow bonding. A laminated tape of gold-plated copper foil acts as a carrier vehicle for semiconductor chips. The foil, etched in the form of leads, is bonded to metallurgical bumps on the chip pads, after which the chip and the attached leads are excised from the tape and bonded to the substrate.
Specifically, identically sized ICs 10 are laterally arranged in parallel and connected to each other and to PCB 12 through the bonding of inner leads of TAB tapes 14 to bonding bumps 16 provided at the pad portions of ICs 10. The TAB leads which both extend vertically between ICs 10 and horizontally over PCB 12, are combined into a small outline package (SOP) which occupies significant device volume. Further, this MCM assembly is only applicable to identically sized ICs and can suffer from electrical noise at high frequency operation due to its TAB leads.
FIG. 1b shows another MCM assembly which electrically connects stacked and identically sized ICs 10 to substrate 18 on a common access plane. This assembly method is described in U.S. Pat. No. 4,706,166, issued on Nov. 10, 1987 to Go, and uses well-known flip-chip technology.
Flip-chip technology allows for the electrical and mechanical connection of a chip to a substrate by inverting and bonding the chip face down to the substrate interconnection pattern. A raised metallic bonding bump is made on each of the chip mounting pads, the bonding bumps corresponding to the conductive land areas on the substrate. The bonding bumps are joined to the conductors on the substrate and bonding is completed using controlled reflow solder techniques or conductive epoxy attachment.
Flip-chip mounting is space and cost efficient because the direct connection between IC layers minimize the area normally taken up by the interconnections between IC layers, and because the technique accomplishes all connections concurrently instead of serially as with wire bonding. Another advantage of this technique is that electrical parasitics are significantly decreased due to short electrical length of the contacts.
U.S. Pat. No. 4,706,166 shows a memory assembly which adhesively binds ICs 10 together and which has exposed leads along an access plane defined by line A. Bonding bumps 16 are formed on the access plane as well as on substrate 18. Both sets of bonding bumps are aligned and bonded together under heat and/or pressure. The MCM is then wire bonded in a housing for external connection. While the device uses space efficient flip-chip connections, the access edge substrate layer and device housing decreases the volume efficiency of the assembly. Edge bonding techniques are relatively costly and only same size ICs can be accommodated by the device.
FIG. 1c shows another flip-chip based MCM assembly, which electrically connects stacked identical IC layers 10 using metal connections within assembly spacers. This type of MCM assembly is exemplified by U.S. Pat. No. 5,128,831, issued on Jul. 7, 1992 to Fox et al. where ICs 10 are all flip-chip bonded to substrates 18. Supporting spacers 20 are positioned between substrates 18 and contain appropriately placed vias 22 that may be connected electrically with substrate vias 24. The package is then placed in a solder bath to fill vias 22 and 24 with molten solder. This type of MCM assembly still requires the use of spacers which appreciably increase the vertical and horizontal dimension of the assembly and thus the overall device volume.
FIG. 1d shows a typical ball grid array MCM as exemplified by U.S. Pat. No. 5,222,014 issued Jun. 22, 1993 to Lin. One IC layer 10 and its carrier substrate 18 is electrically connected to a second IC layer 10' and its carrier substrate 18' using reflowable solder balls 26 which are pre-bumped onto the appropriate surfaces of substrates 18 and 18'. Electrical connections between IC layers 10 and 10' and their respective substrates 18 and 18' are made using conventional wire bonding wires 28 and flip-chip bonding. Interconnections between IC layers 10 and 10' are achieved through vias interconnects 30 and solder balls 26. While each substrate is capable of carrying multiple chips and different sized ICs may be used within the MCM, the device employs volume consuming carrier substrates 18 and 18' and solder balls 26 and encounters noise at high frequency operation.
FIG. 1e shows an MCM assembly with metal-filled through-hole vias, a typical application of which is discussed in U.S. Pat. No. 5,229,647 issued Jul. 20, 1993 to Gnadinger. Vertical interconnection between one silicon wafer 32 and another silicon wafer 32' is achieved using metal-filled through-hole vias 34 and 34' to contact bumps 36 and 36' on adjacent wafers. Although this is an efficient wafer connection method, individual ICs from different manufacturers cannot be used. Further, the device is mounted in a housing which significantly reduces the silicon density of the device.